/************************************************************* * File: mon/regdefs.c * Purpose: Part of core Monitor * Author: Phil Bunce (pjb@carmel.com) * Revision History: * 970304 Start of revision history */ #include /************************************************************* * regdefs.c * This file contains the register definitions for some * of the core MIPS registers. */ RegSpec mips_sr_def[] = { {4,28,"CU",2,0,0}, {1,22,"BEV",2,0,0}, {1,21,"TS",2,0,1}, {1,20,"PE",2,0,1}, {1,19,"CM",2,0,0}, {1,18,"PZ",2,0,0}, {1,17,"SWC",2,0,0}, {1,16,"ISC",2,0,0}, {8,8,"IM&SW",2,0,0}, {1,5,"KUo",2,0,0}, {1,4,"IEo",2,0,0}, {1,3,"KUp",2,0,0}, {1,2,"IEp",2,0,0}, {1,1,"KUc",2,0,0}, {1,0,"IEc",2,0,0}, {0}}; RegSpec mips3_sr_def[] = { {4,28,"CU",2,0,0}, {1,22,"BEV",2,0,0}, {1,20,"SR",2,0,1}, {8,8,"IM&SW",2,0,0}, {2,3,"KSU",2,0,0}, {1,2,"ERL",2,0,0}, {1,1,"EXL",2,0,0}, {1,0,"IE",2,0,0}, {0}}; RegSpec mips_cause_def[] = { {1,31,"BD",2,0,1}, {2,28,"CE",10,0,1}, {6,10,"IP",2,0,1}, {2,8,"SW",2,0,0}, {4,2,"EXCODE",0,excodes,1}, {0}}; RegSpec mips3_cause_def[] = { {1,31,"BD",2,0,1}, {2,28,"CE",10,0,1}, {6,10,"IP",2,0,1}, {2,8,"SW",2,0,0}, {5,2,"EXCODE",0,excodes,1}, {0}}; RegSpec mips_prid_def[] = { {8,8,"IMP",10,0,1}, {8,0,"Rev",10,0,1}, {0}};