4

Exceptions

4.1 Introduction

Exceptions are conditions which alter the normal sequence of instructions, causing the processor to transfer control to a predefined location in memory, the so-called exception vector. In the MIPS1 base architecture there is a single exception vector, the General Exception Vector, whose virtual address depends on the setting of the Status Register's Bootstrap Exception Vector (BEV) bit, as shown in Table 4.1 and described later in this chapter.

The MIPS architecture recognizes seventeen exceptions: eight external interrupts (six hardware interrupts and two software interrupts), and nine program exception conditions (sometimes referred to as 'traps'). The type of exception is encoded in the Exception Code (ExcCode) field of the Cause Register, as shown in Table 4.2.

Table 4.1 General Exception Vector Addresses

                          BEV = 1
                       (Reset State)		   BEV = 0

Virtual Address       Oxbfc0.0180 (kseg1)       0x8000.0080 (kseg0)    
Physical Address      0x1fc0.0180               0x0000.0080           

Table 4.2 ExcCode Field in Cause Register

   ExcCode      Assembler     Exception Type
    Value        Mnemonic  

     0           EXC_INT      External interrupt
     1           -            Reserved
     2           -            Reserved
     3           -            Reserved
     4           EXC_ADEL     Address error (load or instruction fetch)
     5           EXC_ADES     Address error (data store) 
     6           EXC_IBE      Bus error (instruction fetch)
     7           EXC_DBE      Bus error (data load or store) 
     8           EXC_SYS      Syscall instruction
     9           EXC_BP       Breakpoint 
     10          EXC_RI       Reserved instruction
     11          EXC_CPU      Coprocessor Unusable
     12          EXC_OVF      Arithmetic overflow
     13-15                    Not used.

When an exception occurs, the following events take place:

1. The currently executing instruction is aborted, as well as any instructions in the pipeline that have already begun executing.

2. In the Status Register, the Previous Kernel/User Mode and Previous Interrupt Enable bits are copied into the Old Mode and Old Interrupt Enable bits respectively, and the Current Mode and Current Interrupt Enable bits are copied into the Previous Mode and Previous Interrupt Enable bits.

3. The Current Interrupt Enable bit is cleared, which disables all interrupts.

4. The Current Kernel/User Mode bit is cleared, which places the processor in Kernel Mode.

5. If the instruction executing when the exception occurred is in the delay slot of a branch, the Branch Delay (BD) bit in the Cause Register is set.

6. The Exception Program Counter Register (EPC) is set with the address at which the program can be correctly restarted. If the instruction causing the exception is in the delay slot of a branch (BD=1), the EPC is written with the address of the preceding branch or jump instruction. Otherwise, it is written with the address of the instruction that caused the exception, or in the case of an interrupt, with the address of the next instruction to be executed.

7. The Exception Code (ExcCode) field of the Cause Register is written with a number, between 0 and 15, that encodes the type of exception (refer to Table 4.2).

8. If the exception is a Coprocessor Unusable exception, the Cause Register's Coprocessor Error (CE) field is set with the referenced Coprocessor Unit number.

9. If the exception is an Address Error, the address associated with the illegal access is written to the BadVAddr register.

10. The processor then jumps to the General Exception Vector, whose address depends on the setting of the BEV bit: When BEV = 1, the General Exception Vector is mapped to a noncacheable kseg1 address; when BEV = 0, it is mapped to a cacheable kseg0 address (see Table 4.1).

When the exception handler has completed, it uses the address in the EPC register as the return address in a jump, and then executes a Return From Exception (rfe) instruction in the jump's delay slot. The rfe instruction restores the Current and Previous Mode and Interrupt Enable bits to their contents prior to the interrupt, leaving the Old bits unchanged.